1. Field of the Invention
The present invention relates to an interrupt controller for accepting interrupts for a Central Processing Unit (CPU), a computer system having the interrupt controller, and interrupt handling method and storage medium storing program for the interrupt handling method, capable of accepting multiple interrupt request signals.
2. Description of the Related Art
In computer systems, in addition to executing programs sequentially, it is a common method wherein a program being executed is temporarily suspended by an internal or external source, so as to allow another program to be executed. This is termed "interrupt processing" (or simply, an "interrupt"). The temporarily suspended program is restarted after the interrupt processing program has been executed.
In order to realize this type of interrupt processing, at least the following are required: (1) a system for sending an interrupt request to the CPU; (2) a system for suspending the program while preserving the state of the CPU; and (3) a system for notifying the CPU of the start address of the interrupt processing program which processes the requested interrupt. Furthermore, interrupt sources are usually assigned levels (priority levels) in order to prevent important programs being delayed due to interrupt request signals occurring during the execution thereof. Therefore, (4) a level-determining system is also required so that low-level interrupts are not accepted during the execution of high-level processing. And, (5) a system for switching the mask level is required to ensure that, when a high-level interrupt has been generated, interrupts of a lower level than the high-level interrupt are not accepted.
Conventionally, an interrupt controller is connected to the CPU in order to provide these systems. There have been two conventional methods of dividing the functions of the CPU and the interrupt controller.
In a first conventional method, interrupts are executed automatically by the hardware of the CPU and the interrupt controller. This first conventional method will next be explained referring FIG. 1.
Interrupt request signals #1.about.#n are accepted via flip-flops 111 and are each allocated levels 112 and vectors (showing the start addresses of the interrupt processing programs) 114. When one or more of these is activated, an interrupt controller 110 deems the highest level among the levels 112 corresponding to the activated interrupt as an interrupt level signal 113A and notifies the CPU 120 by means of a level detecting circuit 113.
The CPU 120 compares the interrupt level 113A with the mask level 121. When the interrupt level is higher, the CPU 120 saves the present state of the CPU 120 via a bus 130 in a memory 140. In addition, vector request signal 115A becomes valid. Then, a vector selector 115, which is provided within the interrupt controller 110, sends a vector 114 which corresponds to the highest level interrupt request to the bus 130.
The CPU 120 reads out the value of this vector from the bus, calculates from this value the start address of the interrupt processing program and proceeds to execute the interrupt processing program. Moreover, the CPU 120 sets the value of the mask level 121 so as to match the value of the interrupt level.
Thus, by performing much of the processing using the hardware, the first method is capable of high-speed processing.
According to a second conventional method, the CPU has few functions for interrupt processing. Instead, interrupts are realized using the hardware and software of the interrupt controller. This second conventional method will next be explained referring FIG. 2.
When one or more of the interrupt request signals #1.about.#n is activated, the interrupt controller 210 compares the interrupt level of the source of the activation with the mask level 211. When the interrupt level of the source is found to be higher, the interrupt controller 210 activates an interrupt notification signal 210A and sends a request for interrupt processing to the CPU 220.
When an interrupt request signal is activated, the CPU 220 commences execution of an interrupt processing program which is stored in the memory 240. This interrupt processing program first saves the current state in the memory. Then the interrupt processing program reads out interrupt source information 212 from the interrupt controller 210, determines the source of the interrupt request from among interrupt request signals #1.about.#n, and calculates the start address of the interrupt processing program which corresponds to this interrupt source. Then, a value corresponding to the level of this interrupt source is written into the mask level 211, whereafter processing shifts to the start address of the newly calculated interrupt processing program.
Executing much of the processing using programs in this way has advantages of allowing the amount of hardware to be reduced and lowering costs, while offering flexible processing. And, since the CPU state is saved by the program as described above, it is possible to accept other interrupts before saving. However, since the CPU state is destroyed when an interrupt is accepted prior to saving, interrupts are generally prohibited until the CPU state has been preserved.
However, although the first conventional method described above has excellent interrupt response speed (the time from detection of an interrupt request to the commencement of interrupt processing) due to the fact that processing is executed with hardware itself, it does have the disadvantage of inflexible processing. And, although the second conventional method described above needs only a small amount of hardware, much of the processing must be executed using programs. For instance, the source of an interrupt cannot be identified without a program to compare each of the interrupt sources one by one. As a consequence, there is a disadvantage of limited interrupt response speed.